In recent years, the signal processing speed of information processing apparatus, such as servers has been increasing, and there has developed a need to further increase signal transmission speed on circuit boards. To increase the signal transmission speed, the signal transmission frequency must be increased; however increasing the transmission frequency may also result in increasing the signal transmission loss to a non-negligible level even if signals were transmitted over the same distance as before.
For example, in the wiring on a circuit board in a server, as the operating frequency increases, the transmission loss of high-frequency components, due to skin effect, etc., increases to an appreciable level, and the sharpness of signal edges is lost, resulting in a degradation of the received signal level at the receiver end. The degradation of the signal level at the receiver end results in reduced resistance to signal noise and reduced timing margin.
To address this problem caused by the degradation of the signal level at the receiver end, there is proposed a parallel buffer driver comprising a plurality of buffers in parallel (refer to patent document 1). The proposed driver circuit turns on or off the respective parallel buffers according to the signal change pattern, thereby increasing the driving capability of the driver to compensate for the high-frequency transmission loss of signals.
However, as the frequency increases, a slight clock drift can make accurate signal sampling impossible.
Patent document 1: WO2003/084161